This is a short,intermediate level course in Systemverilog HDL and itcovers only the ONE specific topic in it, “the assignment statements”.The objective ofthis course is to teachthe different types of assignment statements in Verilog and Systemverilog, and to map them to the final circuit produced in the IC.Although,it is designed for learning SoC design coding rather than verification,verification engineers are also encouraged to enroll this, as it is teaching one of thefundamental principal in a Hardware Description Language.First, it teaches the different types of assignment statements in Verilog and Systemverilog, and their correct usage so that the intended circuit is generated by the HDL code after synthesis.It includes,Continuous assignmentsProcedural AssignmentsBlocking AssignmentNon Blocking AssignmentsAll of them are explained specific toVerilog as well as Systemverilog. Also, the usage ofall these statementsto produce the basic digital circuits are explained, which are,Combinational circuitsSequential CircuitsFlip FlopLatchNext it teaches the effect of adding flow control statements in the final circuit. Here you will learn what circuit componentswill be generated if youadd,Branching Statementsif-else, caseLooping Statementsfor, while, do whileJumping Statementsdisable, break, continue, returnIf you are an expert, or someone who is already able to map these statements to the circuits,this course is NOT for you. Also, if you are beginnerto Verilog or Systemverilog, this course will NOT teach the basics of programming for those HDLs.To make this course effectivefor you,you must havethe basic knowledge of either Verilog orSystemverilog. You should be able to write simple design and test bench programs in Verilog or Systemverilog, and simulate. If you are not familiar with these, you are encouraged to enroll our basic level course titled “SystemVerilog Beginner: Write Your First Design &TB Modules”.