This is a short,intermediate level course in Systemverilog HDL and itcovers only the few specific topic in it which are useful in design /RTL coding.The objective ofthis course is to teachSystemverilog extensions to Verilog for RTL design coding which are widely used in the VLSI industry. Although,it is designed for learning SoC design coding rather than verification,verification engineers are also encouraged to enroll this, as all of them are useful in test-bench coding as well . This will teach below constructs.Constants & ParametersParameterized ModulesFunctions & TasksEnumerationTypedefStructureInterfaces & ModportsGenerate StatementsIf you are an expert, or someone who is already writing full fledged systemverilog RTL design code, this course is NOT for you. Also, if you are beginnerto Verilog or Systemverilog, this course will NOT teach the basics of programming for those HDLs. To make this course effectivefor you,you must havethe basic knowledge of either Verilog orSystemverilog. You should be able to write simple design and test bench programs in Verilog or Systemverilog, and simulate.